1. Field of the Invention
The present invention relates to a decoder circuit and, in particular, to a structure of a decoder circuit for use to drive word lines of a dynamic randon access memory (DRAM).
2. Description of the Prior Art
It has been known that, in order to increase integration of semiconductor memory, size of semiconductor element tends to be further minimized. Currently, a memory cell of a DRAM is mainly of one transistor-one capacitor type and, in order to reliably write a potential with respect to a storing capacity of the memory cell, it is necessary to supply a write voltage high enough. To this end, word lines connected to gate transistors forming the memory cell must be driven with a potential which is higher than a threshold voltage of this gate transistor. In order to realize this requirement, a decoder circuit for selecting and driving an arbitrary word line is used.
A conventional decoder circuit can be composed generally of a logic circuit responsive to input address signals to provide a signal of a predetermined level and a word line drive transistor whose conduction is controlled by an output of the logic circuit. The word line drive transistor has one of a source and a drain connected to an input terminal of a clock signal for writing, the other connected to a word line and a gate connected to an output of the logic circuit.
In general, the word line drive transistor is an N channel transistor. Therefore, in order to drive the word line with a clock signal, the word line drive transistor must be made conductive by supplying a high level voltage to its gate. For example, when a 5 volts voltage is written in a memory cell using a usual 5 volts power source, the word line voltage must be in the order of 7 volts because a threshold voltage of the gate transistor of the memory cell must be compensated for. Therefore, the clock signal voltage to be supplied to the word line must be as high as 7 volts and thus in order to make the word line drive transistor connected to the word line conductive, a voltage as high as in the order of 9 volts is applied to the gate by means of a bootstrap circuit.
In the current state of art in which thickness of gate oxide film of a transistor is made thinner for high integration requirement and thus breakdown voltage of the element is lowered thereby, such high voltage may cause a degradation of reliability.
In order to solve this problem, it has been proposed to use a P channel transistor as a word line drive transistor so that a word line can be made high voltage without applying such high voltage to a gate of the transistor. That is, the P channel transistor can be made conductive by applying a low level voltage to its gate and, in the above mentioned example, the voltage to be applied to the gate can be reduced to 5 volts at least.
The P channel transistor, however, is formed in an N well provided in a P type substrate and therefore a PN junction is formed between the P type substrate and the N well. Therefore, in order to prevent the PN junction from being forward biased, the N well must be kept at high voltage during the transistor is conductive. As a voltage source for making the N well high voltage, a write clock signal has been used conventionally.
As mentioned above, when a P channel transistor is used to avoid the use of high voltage at a gate thereof, a write clock signal must be applied to not only a word line but also an N well.
When an N channel transistor is used as a word line drive transistor, a load capacity of a clock signal for write includes mainly a capacity of a source of drain diffusion layer of respective transistor, while, when a P channel transistor is used therefor, a capacity of an N well diffusion layer is added thereto, causing a total load capacity of the write clock signal to be several times that for the case where the N channel transistor is used.
It is difficult to drive such large capacitive load at high speed. Therefore, a rate of the write clock signal is lowered necessarily and thus a rising speed of word line potential level is lowered.